1. Field of the Invention
The present invention relates to a structure of a memory device and a fabrication method thereof. More particularly, the present invention relates to a two-bit mask read-only memory (ROM) device and the fabricating method thereof.
2. Background of the Invention
Mask ROM device is a very fundamental type of read-only memory devices, in which a photomask layer is used to define a connection between a metal line and a memory cell or an ion implantation process is used to adjust the threshold voltage to achieve the “on” and “off” of the memory cell. When there are changes in the product of a mask ROM device, no dramatic modification is demanded by the manufacturing process. Only one set of photomask needs to be changed. Therefore, the manufacturing of a mask ROM device is suitable for mass production. Actually, a portion of the manufacturing process can be completed first. The programming of the device can be quickly performed soon after an order is placed to move up the delivery/shipping date.
Currently a two-bit memory cell is being aggressively developed. A two-bit memory cell apparently implies two bits of data are stored in a single memory cell. The structure of this type of memory device is summarized below.
FIG. 1 is a schematic diagram illustrating a cross-sectional view of 2-bit mask ROM device.
Referring to FIG. 1, a conventional 2-bit mask ROM device includes a substrate 100, a gate structure 106, a 2-bit coding implantation region 110, a buried drain region 108, an insulation structure 112 and a word line 114.
The gate structure 106 is arranged on the substrate 100, wherein the gate structure 106 includes a gate conductive layer 104 and an underlying gate oxide layer 102. Further, the buried drain region 108 is disposed beside both sides of the gate structure 106 in the substrate 100 to serve as a bit line.
Moreover, the 2-bit coding implantation region 110 is located beside the side of the gate structure 106 in the substrate 100. A memory cell with the presence of the coding ions implanted in the 2-bit coding implantation region 110 corresponds to a logic state of “1”, while in the absence of coding ions implanted in the 2-bit coding implantation region 110 corresponds to a logic state of “0”.
The insulation structure 112 is disposed on the substrate 100 that is above the buried drain region 108 to isolate the neighboring gate structures 106. Further, a word line 114 is formed on the surface of the gate structures 106 to electrically connect the gate structures 106 along the same row.
Since the dopant concentration in the buried drain region of the conventional a 2-bit mask ROM device is very high, the neighboring memory cells are easily be interfered by the 2-bit mask ROM device. Further, the junction of the buried drain region of a conventional 2-bit mask ROM is connected with the 2-bit coding implantation region, a junction leakage thus easily occurs. Since during the operation of the conventional 2-bit mask ROM device, the neighboring memory cells are easily be interfered and a junction leakage easily occurs, the operation window of a conventional 2-bit mask ROM is smaller.